HMP8156ACNZ【PDF 10/34 页】IC VIDEO ENCODER NTSC/PAL 64MQFP

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Sheet目录1996

6页 7页 8页 9页 [10页]11页 12页 13页 14页

FN4343.5

August 20, 2009

FIGURE 21. REGISTER WRITE PROGRAMMING FLOW

TABLE 11. PRODUCT ID REGISTER

SUB ADDRESS = 00H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-0

Product ID

This 8-bit register specifies the last two digits of the product number. It is a read-only register.

Data written to it is ignored.

54H

S = START CYCLE

P = STOP CYCLE

A = ACKNOWLEDGE

FROM MASTER

FROM ENCODER

0x40 OR

DATA WRITE

DATA

DATA READ

REGISTER

POINTED

TO BY

SUBADDR

REGISTER

POINTED

TO BY

SUBADDR

NA = NO ACKNOWLEDGE

0x41 OR

CHIP ADDR

SUB ADDR

DATA

CHIP ADDR

SUB ADDR

CHIP ADDR

0x43

0x42

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

0x40 OR

0x42

TABLE 12. OUTPUT FORMAT REGISTER

SUB ADDRESS = 01H

BIT

NUMBER

FUNCTION

DESCRIPTION

RESET

STATE

7-5

Video Timing

Standard

000 = (M) NTSC

001 = (M) NTSC with a 0 IRE setup; also called (NSM) NTSC

010 = (B, D, G, H, I) PAL

011 = (M) PAL

100 = (N) PAL

101 = combination (N) PAL; also called (CN) PAL

110 = reserved

111 = reserved

000B

4-3

Output Format

00 = Composite + Y/C

01 = reserved

10 = Composite + RGB (no sync on green)

11 = Composite + RGB (with sync on green)

00B

2-0

Reserved

000B

HMP8154, HMP8156A

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